The present invention relates to semiconductor technology and more particularly to a method of forming trenches with a wide upper portion and a narrow lower portion.
Power trench field effect transistors (FETs) such as power trench MOSFETS and IGBTs are well known in the semiconductor industry. One variety of power trench FETs is the vertically-conducting trench FET, a simplified cross-section view of which is shown in FIG. 1. MOSFET 100 has trenches 111 each including a gate electrode 112 insulated from body regions 114 by gate dielectric 110. Source regions 116 flank each trenches 111. Dielectric cap 120 insulates gate electrodes 112 from overlying metal layer 126. Substrate 102 forms the drain of MOSFET 100.
When MOSFET 100 is biased in the on state, current flows vertically between source regions 116 and substrate 102. The current capability of MOSFET 100 in the on state is a function of the drain to source resistance (Rdson). To improve the current capability of the MOSFET, it is necessary to reduce the Rdson. One way to reduce the Rdson of the trench FET is to increase the trench density (i.e., to increase the number of trenches per unit area). This may be achieved by reducing the cell pitch. However, reducing the cell pitch of trench FETs is limited by the particulars of the FET cell structure and the specific process recipe used to manufacture the FET. Reducing the cell pitch is made further difficult by such limitations of the manufacturing process technology as the minimum critical dimensions the photolithography tools are configured to resolve, the minimum required spacing between different cell regions as dictated by the design rules and the misalignment tolerances.
The different dimensions that determine the minimum cell pitch for trench MOSFET 100 are shown in FIG. 1. Dimension A is the minimum trench width the photolithography tools are configured to resolve, dimension B is the minimum contact opening the photolithography tools are configured to resolve, dimension C is the minimum trench-to-contact spacing dictated by the design rules, and dimension D is the contact registration error tolerance or contact misalignment tolerance. The minimum cell pitch for MOSFET 100 thus equals A+B+2C+2D. Cost effective techniques for reducing the cell pitch are disclosed in U.S. Pat. No. 6,916,745 issued Jul. 12, 2005 to Herrick et al., incorporated herein in its entirety. One aspect of the techniques disclosed in U.S. Pat. No. 6,916,745 is formation of trenches with a wide upper portion and a narrow lower portion. Described hereinafter, in accordance with embodiments of the present invention, are even more cost effective techniques for forming such trenches.